library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;


library lib_ExpoRNS ;


-- Fichier de test de la MMU


------------------------------

entity TEST_RNS is
port(
	signal alpha_reel : out unsigned(31 downto 0) ;
	signal beta1_reel : out unsigned(31 downto 0) ;
	signal beta2_reel : out unsigned(31 downto 0) 
);
end TEST_RNS ;

------------------------------

architecture arch_test_RNS of TEST_RNS is
	
	-- Définition du composant principal
	
	component RNS_dec_unit is
	generic(
		Z_RNS : positive range 1 to 256 ;		-- Nombre de bits du module
		
		N_alpha : positive ;	-- Vecteur de base : OBLIGATOIREMENT de la forme 2^n 
		
		N_beta1 : positive ;	-- Vecteur de base : OBLIGATOIREMENT PAS de la forme 2^n 
		R_beta1 : positive ;
		k_beta1 : positive ;
		
		N_beta2 : positive ;	-- Vecteur de base : OBLIGATOIREMENT de la forme 2^n 
		R_beta2 : positive ;
		k_beta2 : positive
	) ;
	port(
		a : in std_logic_vector(Z_RNS-1 downto 0) ;
		
		alpha : out std_logic_vector(Z_RNS-1 downto 0) ;
		beta1 : out std_logic_vector(Z_RNS-1 downto 0) ;
		beta2 : out std_logic_vector(Z_RNS-1 downto 0)
	) ;
	end component ;
	
	signal input_a : std_logic_vector(31 downto 0) := (others => '0') ;
	
	signal R_beta1_ext : unsigned(31 downto 0) := to_unsigned(1, 32) ;
	signal N_beta1_ext : unsigned(31 downto 0) := to_unsigned(1, 32) ;
	signal R_beta2_ext : unsigned(31 downto 0) := to_unsigned(1, 32) ;
	signal N_beta2_ext : unsigned(31 downto 0) := to_unsigned(1, 32) ;
	
	signal alpha_ext : unsigned(31 downto 0) ;
	signal beta1_ext : unsigned(31 downto 0) ;
	signal beta2_ext : unsigned(31 downto 0) ;
	
BEGIN
	
	RDU : RNS_dec_unit
	generic map(
		Z_RNS => 32 ,
		N_alpha => 256,
		N_beta1 => 255, R_beta1 => 256, k_beta1 => 1 ,
		N_beta2 => 127, R_beta2 => 128, k_beta2 => 1
	)
	port map(
		a => input_a ,
		unsigned(alpha) => alpha_ext ,
		unsigned(beta1) => beta1_ext ,
		unsigned(beta2) => beta2_ext 
	) ;
	
	values_a : process
	begin
		input_a( 15 downto 0 ) <= "0000000000000001" ;
		input_a( 31 downto 16) <= (others =>'0') ;
		wait for 100 ns ;
		input_a( 15 downto 0 ) <= "0000000100010001" ;
		input_a( 31 downto 16) <= (others =>'0') ;
		wait for 200 ns ;
		input_a( 15 downto 0 ) <= "0000000000110001" ;
		input_a( 31 downto 16) <= (others =>'0') ;
		wait for 300 ns ;
		input_a( 15 downto 0 ) <= "0111111100110001" ;
		input_a( 31 downto 16) <= (others =>'0') ;
		wait for 200 ns ;
		
	end process ;
	
	
	
	alpha_reel <= alpha_ext ;
	beta1_reel <= resize( (beta1_ext * R_beta1_ext) mod N_beta1_ext, 32 ) ;
	beta2_reel <= resize( (beta2_ext * R_beta2_ext) mod N_beta2_ext, 32 ) ;
	
end arch_test_RNS ;